Search: in
VIA Nano
VIA Nano in Encyclopedia Encyclopedia
  Tutorials     Encyclopedia     Videos     Books     Software     DVDs  

VIA Nano

The VIA Nano (formerly code-named VIA Isaiah) is a 64-bit CPU for personal computers. The VIA Nano was released by VIA Technologies in 2008 after five years of development[1] by its CPU division, Centaur Technology. This new Isaiah 64-bit architecture was designed from scratch, unveiled on 24 January 2008,[2][3][4][5] and launched on May 29, including low-voltage variants and the Nano brand name.[6] The processor supports a number of VIA-specific x86 extensions designed to boost efficiency in low-power appliances. A dual-core version is expected but has yet to ship.[7][8] Via Technologies showed off a working prototype of its dual-core x86 processor, the Nano DC, at the Computex 2010 exhibition in Taiwan.[9]

Unlike Intel and AMD, VIA uses two distinct development code names for each of its CPU cores. In this case, the codename 'CN' was used in the United States by Centaur Technology. Biblical names are used as codes by VIA in Taiwan, and Isaiah was the choice for this particular processor and architecture. It is expected that the VIA Isaiah will be twice as fast in integer performance and four times as fast in floating-point performance as the previous-generation VIA Esther at an equivalent clock speed. Power consumption is also expected to be on par with the previous-generation VIA CPUs, with thermal design power ranging from 5 W to 25 W.[10] Being a completely new design, the Isaiah architecture was built with support for features like the x86-64 instruction set and x86 virtualization which were unavailable on its predecessors, the VIA C7 line, while retaining their encryption extensions. Several independent tests showed that the VIA Nano performs better than the single-core Intel Atom across a variety of workloads.[11][12][13] In a 2008 Ars Technica test, a VIA Nano gained significant performance after its CPUID changed to Intel, hinting at the possibility that the benchmark software only checks the CPUID instead of the actual features supported by the CPU to choose a code path.[14]

On November 3, 2009, VIA launched the Nano 3000 series. VIA claims that these models can offer a 20% performance boost and 20% more energy efficiency than the Nano 1000 and 2000 series.[15] Benchmarks run by VIA claim that a 1.6 GHz 3000-series Nano can outperform the aging Intel Atom N270 by about 40 54%.[16] The 3000 series adds an SSE4 instruction set, which was first completely introduced in the Intel Core i7. (A subset of the instructions called SSE4.1 was introduced in the second generation of Core 2 processors).

On January 4, 2011, VIA announced the VIA Nano X2 Dual-Core Processor. VIA Nano X2 processors samples are currently available for OEMs and motherboard vendors, with systems featuring the processors expected to arrive in Q1 2011.

VIA Nano X2 Dual-Core Processor is now available in ITX form-factor in the VE-900 motherboard with the 1.4Ghz L4050 model.



VIA Isaiah floorplan
VIA Isaiah floorplan

  • x86-64 instruction set
  • Superscalar out-of-order instruction execution
  • 65 nm manufacturing process
  • Clock speed of 1 GHz to 2 GHz
  • Bus speed of 533 MHz or 800 MHz
  • Support for ECC
  • x86 virtualization (Intel-compatible implementation), deactivated before stepping 3
  • 32 KB L1 cache and 512 KB L2 cache, exclusive
  • Pin-compatible with the VIA C7

Architecture improvements

VIA Isaiah Architecture die plot
VIA Isaiah Architecture die plot

  • Out-of-order and superscalar design: Providing much better performance than its predecessor, the VIA C7 processor, which was in-order. This puts the Isaiah architecture in line with current offerings from AMD and Intel, except for Intel Atom which has an in-order design.
  • Instructions fusion: Allows the processor to combine some instructions as a single instruction, reducing power requirements and giving higher performance (the Atom uses a similar strategy in processing x86 instructions in a more 'whole' manner, rather than breaking them into RISC-like micro-ops).
  • Improved branch prediction: Uses eight predictors in two pipeline stages.
  • CPU cache design: An exclusive cache design means that contents of the L1 cache is not duplicated in the L2 cache, providing a larger total cache.
  • Data prefetch: Incorporating new mechanisms for data-prefetch, including both the loading of a special 64-line cache before loading the L2 cache and a direct load to the L1 cache.
  • Memory access: Merging of smaller stores into larger load data.
  • Execution units: Seven execution units are available, that allows up to seven micro-ops being executed per clock.
    • 2 Integer units
      • One unit (ALU1) is feature complete, while the other (ALU2) lacks some low usage instructions and therefore can be used more often for tasks like address calculations.
    • 2 Store units (VIA refer to this as one for Address Store and another for Data Store)
    • 1 Load unit
    • 2 Media units with 128-bit wide datapath, supporting 4 single precision or 2 double-precision operations.
      • One unit (MEDIA-A) correspond to floating point support, 2-clock latency for single-precision and double-precision add instructions, integer SIMD, encryption, divide and square root.
      • The other unit (MEDIA-B) performs single-precision multiplies, with 3-clock latency for double-precision multiplies.
  • Media computation: Refers to the use of floating point execution units.
    • Using an execution unit for floating point computation and another for multiplication allows the execution of up to four floating point and four multiplies per clock.
    • A new implementation of FP-addition with the lowest latency (in clocks) seen in x86 processors so far.
    • Almost all integer SIMD instructions execute in one clock.
    • Implements MMX, SSE, SSE2, SSE3, SSSE3 multimedia instruction sets
    • Implements SSE4 multimedia instruction set (VIA Nano 3000 series only)
  • Power Management: Besides requiring very low power, many new features are included.
    • Includes a new C6 power state (Caches are flushed, internal state saved, and core voltage is turned off).
    • Adaptive P-State Control: Transition between performance and voltage states without stopping execution.
    • Adaptive Overclocking: Automatic overclocking if there is low temperature in the processor core.
    • Adaptive Thermal Limit: Adjusting of the processor to maintain a user predefined temperature.
  • Encryption: Includes the VIA PadLock engine

See also


External links


cs:VIA Nano de:VIA Nano es:VIA Nano fr:VIA Nano ko: hr:VIA Nano it:VIA Nano lv:VIA Nano ja:VIA Nano pl:VIA Nano pt:VIA Nano ru:VIA Nano sh:VIA Nano zh:VIA Nano

Source: Wikipedia | The above article is available under the GNU FDL. | Edit this article

Search for VIA Nano in Tutorials
Search for VIA Nano in Encyclopedia
Search for VIA Nano in Videos
Search for VIA Nano in Books
Search for VIA Nano in Software
Search for VIA Nano in DVDs
Search for VIA Nano in Store


VIA Nano in Encyclopedia
VIA_Nano top VIA_Nano

Home - Add TutorGig to Your Site - Disclaimer

©2011-2013 All Rights Reserved. Privacy Statement