OpenVera is a Hardware Verification Language developed, and managed by Synopsys. OpenVera(TM) is an interoperable, open hardware verification language for testbench creation. The OpenVera language was used as the basis for the advanced verification features in the IEEE Std. 1800 Systemverilog Standard, for the benefit of the entire verification community including companies in the semiconductor, systems, IP and EDA industries along with verification services. OpenVera remains a widely adopted, evolving and well-supported hardware verification language.
OpenVera is an intuitive easy to learn language that combines the familiarity and strengths of HDLs, C++ and Java, with additional constructs targeted at functional verification making it ideal for developing testbenches, assertions and properties. OpenVera accelerates the creation of a verification environment by providing high-level constructs specifically designed for verification of complex SoCs. Designers create testbenches and assertions using OpenVera and EDA vendors create tools that are automatically interoperable.
OpenVera language reference manual (LRM) can be obtained at no cost, but modifications to the language must go through Synopsys.
Vendors supporting OpenVera