Metastability in electronics is the ability of a digital electronic system to persist for an unbounded time in an unstable equilibrium or metastable state. In metastable states, the circuit may be unable to settle into a stable '0' or '1' logic level within the time required for proper circuit operation. As a result, the circuit can act in unpredictable ways, and may lead to a system failure.
Metastable states are inherent features of asynchronous digital systems, and of systems with more than one independent clock domain. In self-timed asynchronous systems, arbiters are designed to allow the system to proceed only after the metastability has resolved, so the metastability is a normal condition, not an error condition. In synchronous systems with asynchronous inputs, synchronizers are designed to make the probability of a synchronization failure acceptably small. Metastable states are avoidable in fully synchronous systems when the input setup and hold time requirements on flip-flops are satisfied.
In electronics, the flip-flop is a device that is susceptible to metastability. It has two well-defined stable states, traditionally designated 0 and 1, but under certain conditions (see below) it can hover between them for longer than a clock cycle. This condition is known as metastability. Such a metastable "state" is considered a failure mode of the logic design and timing philosophy or implementation.
The most common cause of metastability is violating the flip-flop's setup and hold times. During the time from the setup to the hold time (capture window), the data input of the flip-flop should remain in a stable logic state; a change of the data input in that time will have a probability of setting the flip-flop to a metastable state.
In a typical scenario where data travels from the output of a source flip-flop to the input of target flip-flop, metastability is caused by either:
- the target clock having a different frequency than the source flip-flop, in which case the setup and hold time of the target flip-flop will be violated eventually, or
- the target and source clock having the same frequency, but a phase alignment that causes the data to arrive at the target flip-flop during its setup and hold time. This can be caused by fixed overhead or variations in logic delay times on the worst case path between the two flip-flops, variations in clock arrival times (clock skew), or other causes.
In electronics, an arbiter is a circuit designed to determine which of several signals arrive first. Arbiters are used in asynchronous circuits to order computational activities for shared resources to prevent concurrent incorrect operations. Arbiters are used on the inputs of fully synchronous systems, and also between clock domains, as synchronizers for input signals. Although they can minimize the occurrence of metastability to very low probabilities, all arbiters nevertheless have metastable states, which are unavoidable at the boundaries of regions of the input state space resulting in different outputs.
Synchronous circuit design techniques make digital circuits that are resistant to the failure modes that can be caused by metastability. A clock domain is defined as a group of flip-flops with a common clock. Such architectures can form a circuit guaranteed free of metastability (below a certain maximum clock frequency, above which first metastability, then outright failure occur), assuming a low-skew common clock. However, even then, if the system has a dependence on any continuous inputs then these are likely to be vulnerable to metastable states.
When synchronous design techniques are used, protection against metastable events causing systems failures need only be provided when transferring data between different clock domains or from an unclocked region into the synchronous system. This protection can often take the form of a series of delay flip-flops which delay the data stream long enough for the metastability to have statistically been removed.
Although metastability is well understood and architectural techniques to control it are known, it persists as a failure mode in equipment.
Serious computer and digital hardware bugs caused by metastability have a fascinating social history. Many engineers have refused to believe that a bistable device can enter into a state that is neither true nor false and has a positive probability that it will remain indefinite for any given period of time, albeit with exponentially decreasing probability over time. However, metastability is an inevitable result of any attempt to map a continuous domain to a discrete one. There will always be points in the continuous domain which are equidistant (or nearly so) from the points of the discrete domain, making a decision as to which discrete point to select a difficult and potentially lengthy process. If the inputs to an arbiter or flip-flop arrive almost simultaneously, the circuit most likely will traverse a point of metastability. Metastability remains poorly understood in some circles, and various engineers have proposed their own circuits said to solve or filter out the metastability; typically these circuits simply shift the occurrence of metastability from one place to another. Chips using multiple clock sources are often tested with tester clocks that have fixed phase relationships, not the independent clocks drifting past each other that will be experienced during operation. This usually explicitly prevents the metastable failure mode that will occur in the field from being seen or reported. Current engineering solutions to this problem are often the well-characterized, multi-stage common-clock shift registers discussed in the links below.
↑ Interfacing Two Clock Domains, ASIC World
↑ Chuck Benz Fifos and Ring Buffers
↑ Kleeman, L. and Cantoni, A. "Metastable Behavior in Digital Systems" December 1987 IEEE Design & Test of Computers, 4(6):4-19
↑ Ran Ginosar. "Fourteen Ways to Fool Your Synchronizer" ASYNC 2003.
- Digital Logic Metastability
- Metastability Performance of Clocked FIFOs
- The 'Asynchronous' Bibliography
- Asynchronous Logic
- Efficient Self-Timed Interfaces for Crossing Clock Domains
- Dr. Howard Johnson: Deliberately inducing the metastable state
- Detailed explanations and Synchronizer designs
- Metastability Bibliography
Clock Domain Crossing: Closing the Loop on Clock Domain Functional Inplementation Problems, Cadence Design Systems
- Stephenson, Jennifer. Understanding Metastability in FPGAs. Altera Corporation white paper. July 2009.
- Bahukhandi, Ashirwad. Metastability. Lecture Notes for Advanced Logic Design and Switching Theory. January 2002.
- Cummings, Clifford E. Synthesis and Scripting Techniques for Designing Multi-Asynchronous Clock Designs. SNUG 2001.
- Haseloff, Eilhard. Metastable Response in 5-V Logic Circuits. Texas Instruments Report. February 1997.
- Nystrom, Mika, and Alain J. Martin. Crossing the Synchronous Asynchronous Divide. WCED 2002.
- Patil, Girish, IFV Division, Cadence Design Systems. Clock Synchronization Issues and Static Verification Techniques. Cadence Technical Conference 2004.
- Smith, Michael John Sebastian. Application-Specific Integrated Circuits. Addison Wesley Longman, 1997, Chapter 6.4.1.
- Stein, Mike. Crossing the abyss: asynchronous signals in a synchronous world EDN design feature. July 24, 2003.
- Wakerly, John. Digital Design Principles and Practices. Prentice Hall, 2000.