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Logic level

In digital circuits, a logic level is one of a finite number of states that a signal can have. Logic levels are usually represented by the voltage difference between the signal and ground (or some other common reference point), although other standards exist. The range of voltage levels that represents each state depends on the logic family being used.

In binary logic the two levels are logical high and logical low, which generally correspond to a binary 1 and 0 respectively. Signals with one of these two levels can be used in boolean logic for digital circuit design or analysis.

In three-state logic, an output device can also be high impedance. This is not a logic level, but means that the output is not controlling the state of the connected circuit.


The logic level problem

Interconnecting any two logic families often required special techniques such as additional pull-up resistors or purpose-built interface circuits, since the logic families may use different voltage levels to represent 1 and 0 states, and may have other interface requirements only met within the logic family.

Active state

The use of either the higher or the lower voltage level to represent either logic state is arbitrary and may even be changed at different levels within a system. Active-high and active-low states can be mixed at will: for example, a read only memory integrated circuit may have a chip-select signal that is active-low, but the data and address bits are conventionally active-high. Occasionally a logic design is simplified by inverting the choice of active level (see De Morgan's theorem).

An active-high signal represents a binary digit of 1, or asserted state of a logical condition, by the higher of two voltages. The higher voltage represents a binary 1 or "mark", and the lower voltage represents a binary 0 or "space".

An active-low signal represents a binary digit of 0, or asserted state of a logical condition, by the lower of two voltages.


The name of an active-low signal is written with a bar above it to distinguish it from an active-high signal. For example, the name Q, read "Q bar" or "Q not", represents an active-low signal. Other conventions commonly used are:

  • a leading slash (/Q)
  • a leading lower-case n (nQ)
  • a trailing # (Q#), or
  • an "_B" suffix (Q_B).

The slash convention is also used with signals that have a meaning in both states. For example, it is common to have a read/write line written R/W, indicating that the signal is high in case of a read and low in case of a write.

Many control signals in electronics are active-low signals[1] (usually reset lines, chip-select lines and so on). This stems from the fact that most logic families can sink more current than they can source, so fanout and noise immunity increase. It also allows for wired-OR logic if the logic gates are open-collector/open-drain with a pull-up resistor. Examples of this are the I C bus and the Controller Area Network (CAN),and the PCI Local Bus. RS232 signaling, as used on some serial ports, uses active-low signals.

Logic voltage levels

The two logical states of a wire are usually represented by two different voltages, but current is used in some logic families. A threshold is designed for each logic family. When below that threshold, the wire is "low," when above "high". Intermediate levels are undefined and the behavior of the connected circuits is highly implementation-specific. The problem of the circuit designer is to avoid circumstances that produce intermediate levels, so that all results are predictable.

It is usually to allow some tolerance in the voltage levels used; for example, 0 to 2 volts might represent logic 0, and 3 to 5 volts logic 1. A voltage of 2 to 3 volts would be invalid and would occur only in a fault condition or during a logic level transition, as circuits cannot instantly change voltage levels. However, few logic circuits can detect such a fault, and most will end up interpreting the signal as either a 0 or a 1 input, unpredictably and possibly inconsistently.

Combinational circuit outputs also take longer to settle to a final state when an input is close to the invalid middle range, and in a synchronous circuit, this can lead to a propagation of metastability. A clock domain crossing is one situation commonly faced by digital designers where metastability is likely and must be handled carefully.

Examples of binary logic levels:
Technology L voltage H voltage Notes
CMOS 0 V to VDD/2 VDD/2 to VDD VDD = supply voltage
TTL 0 V to 0.8 V 2 V to VCC VCC = 5 V 10%
ECL VEE to 1.4 V 1.2 V to 0 V VEE is about 5.2 V; VCC=Ground

Nearly all digital circuits use a consistent logic level for all internal signals however, that level varies widely from one system to another. A level shifter connects one digital circuit that uses one logic level to another digital circuit that uses another logic level. Often 2 level shifters are used, one at each system: A "line driver" converts from internal logic levels to standard interface line levels; a "line receiver" converts from interface levels to internal voltage levels. The most common agreed-upon voltage levels are the TTL logic levels; almost as common is the RS-232 voltage levels.

The voltage levels used internally are called the "logic level", while the voltage levels used externally are called the "line level". In particular, when connecting a system that uses TTL levels internally to a RS-232 cable, the TTL levels are the "logic level". When connecting a system that uses 3.3 V CMOS levels internally to a IEEE 1284 bus, the TTL levels are the "line level".

See also

External links


de:Logikpegel it:Logica negativa ms:Aras logik ja: zh:

Source: Wikipedia | The above article is available under the GNU FDL. | Edit this article

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